1. Field of the Invention
The present invention relates to a semiconductor integrated device having insulated gate field effect transistors which are well known in general as MOSICs, and a fabrication method thereof, and in particular, to a short channel MOSIC for high-speed operation and with high reliability.
2. Description of the Prior Art
In a semiconductor integrated circuit, the lower supply voltage of MOSFETs is a constant technical requirement associated with miniaturizing the transistor size. For instance, the supply voltage decreases successively from 5.0 v to 4.0 v, and from 4.0 v to 3.3 v as the gate length decreases from 1 .mu.m to 0.8 .mu.m, and from 0.8 .mu.m to 0.5 .mu.m, respectively. This may be explained by the fact that scaling-down of the gate length, without decreasing the supply voltage, would lead to an increase of an internal electric field of MOSFETs, which results in degradation of the device characteristics by unfavorable phenomena such as the punch-through breakdown, drain-induced-barrier-lowering (DIBL), and hot-carrier effect.
These phenomena can be indeed avoided by lowering a drain voltage with a decreased supply voltage, but an effective gate voltage (V.sub.g -V.sub.th) also decreases inevitably, which eventually lowers the saturated drain current to degrade driving ability of MOSFETs, because the threshold voltage (V.sub.th) is still kept constant without any lowering under an operating condition of the saturated region.
For the above reason, a technique has been desired that can lower the threshold voltage (V.sub.th) by decreasing an impurity concentration in a channel region while keeping a necessary punch-through breakdown voltage under an operating condition of a supply voltage particularly below 3.3 v. To accomplish this purpose, several efforts have been made, such as a low-impurity channel MOS transistor disclosed by M. AOKI in Tech. Digest Paper of IEEE IEDM, 939-941 (1990), and also a short-channel MOSFET with a buried doped layer disclosed by H. TAKEDA at The Spring meeting of the Japan Society of Applied Physics 28P-T-2, 1991. Although these efforts have achieved only a limited success for either a short-channel effect or punch-through breakdown, both efforts have substantial disadvantages in controlling process conditions which may result in poor reliability in device characteristics.